The present invention relates to electrical circuits, and more particularly to a circuit and method for providing an improved pre-amplifier scheme for high speed analog-to-digital converters.
The non-ideal characteristics in data conversion interfaces become more apparent for devices that are designed for high precision in contrast to lower precision devices. Mismatch, nonlinearity and finite intrinsic gain are some of the effects that limit resolution of CMOS and bipolar technology in analog-to-digital conversion (ADC) devices. It is common to correct these effects by employing circuit and/or algorithmic techniques. These techniques can be utilized on individual components in addition to the overall architecture of the device to provide input/output characteristics that approach an ideal. Circuits and algorithms employing these techniques conventionally require a dedicated period for cancellation or calibration, thus, complicating the timing scheme of the overall system.
A number of methods currently exist to enhance the precision or relax speed-precision trade-offs of data acquisition systems, such as comparator and operational amplifier offset cancellation, DAC and ADC calibration, and range overlap with digital correction. Offset cancellation in high-precision systems are crucial in CMOS devices because of the large mismatches of CMOS devices. Offset cancellation is also important in bipolar and BiCMOS devices for resolutions above 10 bits. The need for reliable offset cancellation has led to auto-zero techniques in CMOS and BiCMOS comparators, where the offset is periodically sensed, stored and added to the input in such a way as to cancel the offset. The purpose is to minimize the input offset contributed by the pre-amplifier and the latch without compromising other aspects of the performance of the device.
FIG. 1 illustrates a prior art fully-differential comparator device 10 conventionally employed in high speed ADC designs. The comparator device includes a pre-amplifier 12 with a negative input terminal, a positive input terminal, a positive output terminal and a negative output terminal. A first feedback loop 15 couples the negative input terminal to the positive output terminal and a second feedback loop 17 couples the positive input terminal to the negative output terminal. A first capacitor 26 is coupled to the negative input terminal of the pre-amplifier 12 on a right side and a pair of switches 20 and 22 on a left side. A second capacitor 32 is coupled to the positive input terminal of the pre-amplifier 12 on a right side and a pair of switches 28 and 30 on a left side. The switch 20 is coupled to a first voltage input signal (VIN+) and the switch 28 is coupled to a second voltage input signal (VINxe2x88x92). The switch 22 is coupled to a first voltage reference signal (VREF+) and the switch 30 is coupled to a second voltage reference signal (VREFxe2x88x92). The pre-amplifier 12 is followed by a latch 14.
During an auto-zero cycle (e.g., typically, 50 ns-100 ns), the reference voltages VREF+ and VREFxe2x88x92 are connected to the left sides of the capacitors 26 and 32, respectively, while the feedback loops 15 and 17 are connected around the pre-amplifier 12 by closing switches 22, 30, 16 and 18. The voltage stored on the capacitors 26 and 32 are equal to the respective reference voltages minus the pre-amplifier""s common-mode voltage. During the conversion cycles (e.g., typically 100 xcexcs-400 xcexcs), the feedback loops 15 and 17 around the pre-amplifier 12 are opened, and the left sides of the capacitors 26 and 32 are connected to the comparator input signals (VIN+, VINxe2x88x92) instead of the reference signals (VREF+, VREFxe2x88x92). The input node of the pre-amplifier 12 receives the input signal subtracted by the reference voltage. Then the input signal of the pre-amplifier 12 is amplified and fed to the latch 14. The above scheme also cancels the offset of the pre-amplifier 12, since the offset voltage is pre-stored on the capacitors 26 and 32 during the auto-zero cycle, and is cancelled during the conversion cycle. Therefore the key of this method is that the reference voltage and the offset voltage (VREF+VOFFSET) held on the capacitors 26 and 32 must not be changed during the conversion cycle.
However, there is a problem of VREF+VOFFSET leakage from the capacitors 26 and 32, which makes the conventional scheme in FIG. 1 not work properly for all device types. For extremely high speed ADC operation (e.g., 1.28 GSample/s), high-speed devices have to be used as the input device of the pre-amplifier 12. The high-speed device has a reduced feature size, particularly its gate oxide layer thickness and thus it can only withstand a lower gate voltage. However, these devices typically experience gate current leakage during the conversion cycle causing leakage in the storage capacitors 26 and 32. The leakage in the storage capacitors 26 and 32 causes attenuation of the offset voltage of the pre-amplifier 12 and the reference voltage, resulting in unacceptable readings for high resolution ADCs.
In view of the above, it is apparent that there is an unmet need for improvements in the above differential comparator device for high speed ADCs.
The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. A circuit and a method is provided that facilitates for improved performance of a differential comparator device for a very high-speed analog-to-digital converter device. The present invention employs an input offset storage (IOS) technique to compensate for an offset voltage of a pre-amplifier device in the differential comparator device. A reference voltage and an offset voltage are stored on capacitors coupled to the inputs of the differential comparator device during an auto-zero cycle. A source follower is placed between each capacitor and the inputs to the pre-amplifier device. The source followers are selected to prevent leakage of the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the storage capacitors in the conversion mode.
In one aspect of the invention, high-speed devices (e.g., 1.2 volt devices) are utilized in the differential pre-amplifier device. Additionally, an n-type source follower which employs a 3.3 volt device is placed between each capacitor and the inputs to the pre-amplifier device. The 3.3 volt device used in the n-type source followers have substantially no gate to source leakage current. The switches utilized in the feedback loops are also selected to be 3.3 volt NMOS devices due to the fact that they have substantially no leakage that would cause reduction of the offset voltage and the reference voltages stored on the storage capacitors during the auto-zero mode. Since there is a DC level shift caused by the 3.3 volt n-type source followers, a p-type source follower is placed in each of the feedback loops to compensate for the DC level shift, and to assure that the input signal into the pre-amplifier device remains below a 1.2 volt swing.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention, when considered in conjunction with the drawings.